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CMOS 3NAND Logic Semiconductor Design
IP Report
Print Profile(1)
0.16mm layer, 2 walls, 15% infill
Designer
4 h
1 plate
Open in Bambu Studio
Boost
2
10
0
0
6
2
Released
Description
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Model of a Logic Semiconductor Layout. This layout corresponds to a 3-NAND (NOT AND) design with 6 transistors. The source is indicated in the design
Supports are a bit annoying to remove. One could also print it half and half and glue it together. That should be easy to implement with the 3fm file
License
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